The present invention relates to a semiconductor device, and more particularly, to a gate structure and a method for fabricating the gate structure.
In general, as complementary metal-oxide semiconductor (CMOS) devices have become highly integrated, gate pitch has decreased. Certain limitations exist when gate electrodes and gate insulation layers are formed using conventional CMOS process and materials. For this reason, it is desirable to develop new materials that can replace the conventional materials.
In the conventional CMOS process, a polysilicon layer doped with an N-type impurity is used to form gates of N-channel metal-oxide semiconductor (NMOS) and P-channel metal-oxide semiconductor (PMOS) devices. Thus, NMOS devices commonly show surface channel characteristics, while PMOS devices commonly show buried channel characteristics. Due to the buried channel characteristics, PMOS devices are prone to a short channel effect when widths of gates are reduced to a certain level (e.g., 100 nm or less).
In one attempt to overcome the above limitation in fabricating a CMOS device with a short channel length, a dual polysilicon gate structure is suggested by forming gate electrodes of NMOS devices and PMOS devices using N-type impurity-doped polysilicon and P-type impurity-doped polysilicon, respectively. In particular, the dual polysilicon gate structure allows the PMOS devices to have surface channel characteristics, while helping to prevent the short channel effect.
FIG. 1 illustrates a simplified view of a conventional dual polysilicon gate structure. A gate oxide layer 12 is formed on a substrate 11 including PMOS and NMOS regions. The gate oxide layer 12 is formed of silicon oxynitride (SiON). In the NMOS region, a gate structure including a polysilicon layer 13A and a metal electrode 14 is formed on the gate oxide layer 12. The polysilicon layer 13A is highly doped with an N+-type impurity such as phosphorus (P). In the PMOS region, another gate structure including another polysilicon layer 13B and the metal electrode 14 is formed on the gate oxide layer 12. The polysilicon layer 13B is highly doped with a P+-type impurity such as boron (B).
However, the dual polysilicon gate structure illustrated in FIG. 1 has several limitations. For instance, boron doped onto the P+-type polysilicon layer 13B usually penetrates into the channel region in the PMOS region, and this event is likely to cause the threshold voltage to fluctuate. Reference numeral 15A denotes this penetration event. Also, boron doped onto the P+-type polysilicon layer 13B may diffuse out toward the metal electrode 14 as reference numeral 15B illustrates. This out-diffusion of boron may result in a polysilicon depletion effect (PDE), which may degrade the characteristics of the device. Nitriding the surface of the gate oxide layer 12 may reduce the effects associated with the boron penetration 15A into the channel region. However, an effective method that can prevent the PDE has not yet been introduced.
FIG. 2 illustrates a graph of gate voltage versus capacitance of PMOS and NMOS devices in the conventional dual polysilicon gate structure. More specifically, FIG. 2 shows the comparative results of the inversion capacitance of the PMOS and NMOS devices.
Due to the PDE resulting from the boron diffusing out toward the metal electrode 14, the capacitance of the PMOS device is less than that of the NMOS device. This result means that the capacitance effective thickness of the gate oxide layer 12 increases. In such a case, a sub-100 nm gate structure may have a large fluctuation in threshold voltage, and thus, device characteristics are likely to be degraded.
The conventional gate structure may have the following disadvantages. Metal electrodes in the polysilicon gates of memory devices such as dynamic random access memories (DRAMs) are generally formed of tungsten silicide (WSi). However, tungsten (W) receives more attention than WSi as a material for gate electrodes when high operation speeds are desired. Gate structures in CMOS devices using W are often called W-dual polysilicon gate structures.
However, for a gate structure including W and polysilicon, which are in direct contact, a reaction that produces tungsten silicide may occur during the thermal treatment. Thus, a volume expansion, which often leads to a stress reaction, may be observed. Consequently, an additional structure that can function as a diffusion barrier is generally required between the tungsten and polysilicon of the gate structure.